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8mx72 bits pc100 sdram unbuffered microdimm based on 8mx16 sdram with lv ttl, 4 banks & 4k refresh this document is a general product descrip tion and is subject to change without notice. hynix semiconductor inc. does not assum e any re- sponsibility for use of circuits descr ibed. no patent licenses are implied. rev. 0.1/may. 02 1 hym71v8m755hc(l)fu6 series description the hym71v8m755hctu6 series are 8mx72bits synchr onous dram modules. the modules are composed of five 8mx16bits cmos synchronous drams in 54ball fbga pack age, one 2kbit eeprom in 8pin tssop package on a 144pin glass-epoxy printed circuit board. the hym71v8m755hcfu6 series are dual in-line memory modul es suitable for easy interchange and addition of 64mbytes memory. the hym71v8m755hcfu6 series are fully synchronous op eration referenced to the positive edge of the clock . all inputs and outputs are synchronized with the rising edge of the cl ock input. the data paths are internally pipelined to achieve very high bandwidth. features ? pc100mhz support ? 144pin sdram micro so dimm ? serial presence detect with eeprom ? 1.00? (25.40mm) height pcb with double sided compo- nents ? single 3.3 0.3v power supply ? all device pins are compat ible with lvttl interface ? data mask function by dqm ? sdram internal banks : four banks ? module bank : one physical bank ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4 or 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency internal bank ref. power sdram package plating hym71v8m755hcfu6-8 125mhz 4 banks 4k normal fbga gold hym71v8m755hcfu6-p 100mhz HYM71V8M755HCFU6-S 100mhz hym71v8m755hclfu6-8 125mhz low power hym71v8m755hclfu6-p 100mhz hym71v8m755hclfu6-s 100mhz
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 2 hym71v8m755hc(l)fu6 series pin description pin pin name description ck0 clock inputs the system clock input. all other input s are registered to the sdram on the rising edge of clk cke0 clock enable controls internal clock signal and w hen deactivated, the sdram will be one of the states among power down, suspend or self refresh /s0 chip select enables or disables all inputs except ck, cke and dqm ba0, ba1 sdram bank address selects bank to be activated during /ras activity selects bank to be read/written during /cas activity a0 ~ a11 address row address : ra0 ~ ra11, column address : ca0 ~ ca8 auto-precharge flag : a10 /ras, /cas, /we row address strobe, column address strobe, write enable /ras, /cas and /we define the operation refer function truth table for details dqm0~dqm7 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq63 data input/output multiplexed data input / output pin cb0 ~ cb7 data input/output check bits vcc power supply (3.3v) power supply for internal circuits and input buffers v ss ground ground scl spd clock input serial presence detect clock input sda spd data input/output serial presence detect data input/output sa0~2 spd address input serial presence detect address input wp write protect for spd write protect for serial presence detect on dimm nc no connection no connection
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 3 hym71v8m755hc(l)fu6 series pin assignments front side back side front side back side pin no. name pin no. name pin no. name pin no. name 1 vss 2 vss 71 nc 72 nc 3dq04dq3273 nc74*ck1 5 dq1 6 dq33 75 vss 76 vss 7dq28dq3477 nc78nc 9 dq3 10 dq35 79 nc 80 nc 11 vcc 12 vcc 81 vcc 82 vcc 13 dq4 14dq3683dq1684dq48 15 dq5 16dq3785dq1786dq49 17 dq6 18dq3887dq1888dq50 19 dq7 20dq3989dq1990dq51 21 vss 22 vss 91 vss 92 vss 23 dqm0 24 dqm4 93 dq20 94 dq52 25 dqm1 26 dqm5 95 dq21 96 dq53 27 vcc 28 vcc 97 dq22 98 dq54 29 a0 30 a3 99 dq23 100 dq55 31 a1 32 a4 101 vcc 102 vcc 33 a2 34 a5 103 a6 104 a7 vss 36 vss 105 a8 106 ba0 35 37 dq8 38 dq40 107 vss 108 vss 39 dq9 40 dq41 109 a9 110 ba1 41 dq10 42 dq42 111 a10 112 a11 43 dq11 44 dq43 113 vcc 114 vcc 45 vcc 46 vcc 115 dqm2 116 dqm6 47 dq12 48 dq44 117 dqm3 118 dqm7 49 dq13 50 dq45 119 vss 120 vss 51 dq14 52 dq46 121 dq24 122 dq56 53 dq15 54 dq47 123 dq25 124 dq57 55 vss 56 vss 125 dq26 126 dq58 57 nc 58 nc 127 dq27 128 dq59 59 nc 60 nc 129 vcc 130 vcc voltage key 131 dq28 132 dq60 133 dq29 134 dq61 61 ck0 62 cke0 135 dq30 136 dq62 63 vcc 64 vcc 137 dq31 138 dq63 65 /ras 66 /cas 139 vss 140 vss 67 /we 68 nc 141 sda 142 scl 69 /s0 70 nc 143 vcc 144 vcc note : * ck1 are connected with terminat ion r/c (refer to the block diagram)
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 4 hym71v8m755hc(l)fu6 series block diagram /s0 ba0-ba1 : sdrams u0 - u4 a0 - an : sdrams u0 - u4 /ras : sdrams u0 - u4 /cas : sdrams u0 - u4 cke0 : sdrams u0 - u4 /we : sdrams u0 - u4 u0 /cs ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm0 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqm1 u1 /cs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqm2 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqm3 u3 /cs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqm4 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqm5 u4 /cs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqm6 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqm7 serial pd a0 a1 a2 sa0 sa1 sa2 scl wp sda ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqn every dq pin of sdrams 10 ohm 10 ohm 10 ohm ck0 ck1 u0 - u4 10 pf u2 /cs ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dqm1 /s0 ba0-ba1 : sdrams u0 - u4 a0 - an : sdrams u0 - u4 /ras : sdrams u0 - u4 /cas : sdrams u0 - u4 cke0 : sdrams u0 - u4 /we : sdrams u0 - u4 u0 /cs ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm0 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqm1 u0 /cs ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm0 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqm1 u1 /cs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqm2 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqm3 u3 /cs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqm4 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqm5 u4 /cs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqm6 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqm7 u3 /cs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqm4 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqm5 u4 /cs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqm6 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqm7 serial pd a0 a1 a2 sa0 sa1 sa2 scl wp sda serial pd a0 a1 a2 sa0 sa1 sa2 scl wp sda ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqn every dq pin of sdrams 10 ohm 10 ohm 10 ohm ck0 ck1 u0 - u4 10 pf u2 /cs ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dqm1 u2 /cs ldqm dqo dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dqm1 note : 1. the serial resistor values of dqs are 10ohms 2. the padding capacitance of termination r/c for ck1 is 10pf
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 5 hym71v8m755hc(l)fu6 series serial presence detect byte number function description function value note -8 -p -s -8 -p -s byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 12 0ch 1 byte4 # of column addresses on this assembly 9 09h byte5 # of module banks on this assembly 1 bank 01h byte6 data width of th is assembly 72 bits 48h byte7 data width of this assembly (continued) - 00h byte8 voltage interface standar d of this assembly lvttl 01h byte9 sdram cycle time @/cas latency=3 8ns 10ns 10ns 80h a0h a0h byte10 access time from cloc k @/cas latency=3 6ns 6ns 6ns 60h 60h 60h byte11 dimm configuration type ecc 02h byte12 refresh rate/type 15.625us / self refresh supported 80h byte13 primary sdram width x16 10h byte14 error checking sdram width x16 10h byte15 minimum clock delay back to back random column address tccd = 1 clk 01h byte16 burst lenth supported 1,2,4,8,full page 8fh 2 byte17 # of banks on each sdram device 4 banks 04h byte18 sdram device at tributes, /cas lataenc y /cas latency=2,3 06h byte19 sdram device attributes, /cs lataency /cs latency=0 01h byte20 sdram device attributes, /we lataency /we latency=0 01h byte21 sdram module at tributes neither buffered nor registered 00h byte22 sdram device attributes, general +/- 10% voltage tolerence, burst read single bit write, precharge all, auto precharge, early ras precharge 0eh byte23 sdram cycle time @/ca s latency=2 8ns 10ns 12ns a0h a0h c0h byte24 access time from cloc k @/cas latency=2 6ns 6ns 6ns 60h 60h 60h byte25 sdram cycle time @/cas latency=1 - - - 00h 00h 00h byte26 access time from cl ock @/cas latency=1 - - - 00h 00h 00h byte27 minimum row precharge time (trp) 20ns 20ns 20ns 14h 14h 14h byte28 minimum row active to row active delay (trrd) 16ns 20ns 20ns 10h 14h 14h byte29 minimum /ras to /cas delay (trcd) 20ns 20ns 20ns 14h 14h 14h byte30 minimum /ras pulse width (tras) 48ns 50ns 50ns 30h 32h 32h byte31 module bank density 64mb 10h byte32 command and address signal input setup time 2ns 2ns 2ns 20h 20h 20h byte33 command and address signal input hold time 1ns 1ns 1ns 10h 10h 10h byte34 data signal input setup time 2ns 2ns 2ns 20h 20h 20h byte35 data signal input hold time 1ns 1ns 1ns 10h 10h 10h byte36 ~61 superset information (may be used in future) - 00h byte62 spd revision intel spd 1.2b 12h 3, 8 byte63 checksum for byte 0~62 - e1h 27h 2fh byte64 manufacturer jedec id code hynix jeded id adh byte65 ~71 ....manufacturer jedec id code unused ffh byte72 manufacturing location hsi(korea area) hsa (united states area) hse (europe area) hsj (japan area) hss(singapore) asia area 0*h 1*h 2*h 3*h 4*h 5*h 9
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 6 hym71v8m755hc(l)fu6 series byte number function description function value note -8 -p -s -8 -p -s byte73 manufacturer?s part number (component) 7 (sdram) 37h 4, 5 byte74 manufacturer?s part number (128mb based) 1 31h 4, 5 byte75 manufacturer?s part number (voltage interface) v (3.3v, lvttl) 56h 4, 5 byte76 manufacturer?s part number (memory width) 8 38h 4, 5 byte77 manufacturer?s part number (module type) m (so dimm) 4dh 4, 5 byte78 manufacturer?s part number (data width) 7 37h 4, 5 byte79 ....manufacturer?s part number (data width) 5 35h 4, 5 byte80 manufacturer?s part number (refresh, sdram bank) 5 (4k refresh, 4banks) 35h 4, 5 byte81 manufacturer?s part number (manufacturing site) h 41h 4, 5 byte82 manufacturer?s part number (package type) c 54h 4, 5 byte83 manufacturer?s part number (package type) f 46h 4, 5 byte84 manufacturer?s part number (module type) u(micro based) 55h 4, 5 byte85 manufacturer?s part number (component configuration) 6 (x16 based) 36h 4, 5 byte86 manufacturer?s part number (hyphent) - (hyphen) 2dh 4, 5 byte87 manufacturer?s part number (min. cycle time) 8 p s 38h 50h 53h 4, 5 byte88 ~90 manufacturer?s part number blanks 20h 4, 5 byte91 revision code (for component) process code - 4, 6 byte92 ....revision code (for pcb) process code - 4, 6 byte93 manufacturing date year - 3, 6 byte94 ....manufacturing date work week - 3, 6 byte95 ~98 assembly serial number serial number - 6 byte99 ~125 manufacturer specific data (may be used in future) none 00h byte126 system frequency support 100mhz 64h 7, 8 byte127 intel specification details for 100mhz support refer to note7 8fh 8fh 8dh 7, 8 byte128 ~256 unused storage locations - 00h continued note : 1. the bank address is excluded 2. 1, 2, 4, 8 for interleave burst type 3. bcd adopted 4. ascii adopted 5. basically hynix writes part no. except for ?hym? in by te 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. not fixed but dependent 7. ck0 connected to dimm, tbd juncti on temp, cl2(3) support, intel defined concurrent auto precharge support 8. refer to intel sp d specification 1.2b byte 83~88 for l-part byte number function description function value note -8 -p -s -8 -p -s byte82 manufacturer?s part number (power) l4ch4, 5 byte83 manufacturer?s part number (package type) t 54h 4, 5 byte84 manufacturer?s part number (module type) u 55h 4, 5 byte85 manufacturer?s part number (component configuration) 6 (x16 based) 36h 4, 5 byte86 manufacturer?s part number (hyphent) - (hyphen) 2dh 4, 5 byte87 manufacturer?s part number (min. cycle time) 8 p s 38h 50h 53h 4, 5 9. refer to hynix web site
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 7 hym71v8m755hc(l)fu6 series absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. dc operating condition (t a =0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3.v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration. ac operating test condition (t a =0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.output load to measure access times is equivalent to two ttl gates and one capacitor (50pf). for details, refer to ac/dc outp ut load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 4w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il -0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement c l 50 pf 1
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 8 hym71v8m755hc(l)fu6 series capacitance (ta=25 c , f=1mhz) output load circuit parameter pin symbol -8/p/s unit min max input capacitance ck0 c i1 20 40 pf cke0 c i2 15 35 pf /s0 c i3 15 35 pf a0~11, ba0, ba1 c i4 15 35 pf /ras, /cas, /we c i5 15 30 pf dqm0~dqm7 ci 6 515pf data input / output capacitance dq0 ~ dq63 , cb0 ~ cb7 c i/o 515pf vtt=1.4v rt=250 ? 50pf output 50pf output dc output load circuit ac output load circuit
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 9 hym71v8m755hc(l)fu6 series dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 dc characteristics ii note : 1. i dd1 and i dd4 depend on output loading and cycl e rates. specified values are measured with the output open 2. min. of trrc (refresh ras cycle ti me) is shown at ac characteristics ii 3.hym71v8m755hcfu6-8/p/s 4. hym71v8m755hclfu6-8/p/s parameter symbol min. max unit note input leakage current i li -4 4 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4vi ol = +2ma parameter symbol test condition speed unit note -8 -p -s operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 400 400 400 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 8 ma i dd2ps cke v il (max), t ck = 8 precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other pins v dd -0.2v or 0.2v 80 ma i dd2ns cke v ih (min), t ck = input signals are stable. 40 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 28 ma i dd3ps cke v il (max), t ck = 28 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other pins v dd -0.2v or 0.2v 160 ma i dd3ns cke v ih (min), t ck = input signals are stable. 160 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 440 400 400 ma 1 cl=2 400 400 360 auto refresh current i dd5 t rrc t rrc (min), all banks active 800 ma 2 self refresh current i dd6 cke 0.2v 8.2 ma 3 4ma4
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 10 hym71v8m755hc(l)fu6 series ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter 2.access times to be measured with input si gnals of 1v/ns edge rate, from 0.8v to 2.0v if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter parameter symbol -8 -p -s unit note min max min max min max system clock cycle time cas latency = 3 tck3 8 1000 10 1000 10 1000 ns cas latency = 2 tck2 10 10 12 ns clock high pulse width tchw 3 - 3 - 3 - ns 1 clock low pulse width tclw 3 - 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 6 - 6 - 6 ns 2 cas latency = 2 tac2 - 6 - 6 - 6 ns data-out hold time toh 3 - 3 - 3 - ns data-input setup time tds 2 - 2 - 2 - ns 1 data-input hold time tdh 1 - 1 - 1 - ns 1 address setup time tas 2 - 2 - 2 - ns 1 address hold time tah 1 - 1 - 1 - ns 1 cke setup time tcks 2 - 2 - 2 - ns 1 cke hold time tckh 1 - 1 - 1 - ns 1 command setup time tcs 2 - 2 - 2 - ns 1 command hold time tch 1 - 1 - 1 - ns 1 clk to data output in low-z time tolz 1 - 1 - 1 - ns clk to data output in high-z time cas latency = 3tohz33 63636ns cas latency = 2tohz23 63636ns
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 11 hym71v8m755hc(l)fu6 series ac characteristics ii note : 1. a new command can be given trrc after self refresh exit parameter symbol -8 -p -s unit note min max min max min max ras cycle time operation trc 68 - 70 - 70 - ns auto refresh trrc 68 - 70 - 70 - ns ras to cas delay trcd 20 - 20 - 20 - ns ras active time tras 48 100k 50 100k 50 100k ns ras precharge time trp 20 - 20 - 20 - ns ras to ras bank active delay trrd 16 - 20 - 20 - ns cas to cas delay tccd 1 - 1 - 1 - clk write command to data-in delay twtl 0 - 0 - 0 - clk data-in to precharge command tdpl 1 - 1 - 1 - clk data-in to active command tdal 4 - 3 - 3 - clk dqm to data-out hi-z tdqz 2 - 2 - 2 - clk dqm to data-in mask tdqm0-0-0-clk mrs to new command tmrd 2 - 2 - 2 - clk precharge to data output hi-z cas latency = 3tproz33-3-3-clk cas latency = 2tproz22-2-2-clk power down exit time tpde 1-1-1-clk self refresh exit time tsre 1 - 1 - 1 - clk 1 refresh time tref - 64 - 64 - 64 ms
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 12 hym71v8m755hc(l)fu6 series device operating option table hym71v8m755hc(l)fu6-8 hym71v8m755hc(l)fu6-p hym71v8m755hc(l)fu6-s cas latency trcd tras trc trp tac toh 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 13 hym71v8m755hc(l)fu6 series command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank address, ra = row address, ca = column address, opcode = operand code, nop = no operation 3. the burst read sigle write mode is enter ed by programming the write burst mode bit (a9) in the mode register to a logic 1. command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-write h x l l l l x a9 pin high (other pins op code) mrs mode self refresh 1 entry h l lllhx x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
pc100 sdram unbuffered microdimm rev. 0.1/may. 02 14 hym71v8m755hc(l)fu6 series package demension tolerances : 0.13 unless otherwise specified units : mm 5.00 1.80 38.00 25.40 1.00 min . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . 42.00 1.00 min 15.00 0.875 2.50min detail z . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 37.00 1.00 r1.00 0.10 4.00 0.10 1.80 0.25 max 0.50 0 .37 0.03 2.00 min 0.80 0.08 3.81 max detail z r1.00 tolerances : 0.13 unless otherwise specified units : mm 5.00 1.80 38.00 25.40 1.00 min . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . 42.00 1.00 min 15.00 0.875 2.50min detail z . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 37.00 1.00 r1.00 0.10 4.00 0.10 1.80 0.25 max 0.50 0 .37 0.03 2.00 min 0.80 0.08 3.81 max detail z r1.00

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